Hello,

I have another issue with the ethmac_latest code. The project uses a wishbone with 32 bit bus. For that I use a 32-bit-bus RAM. When I save my frame into RAM I should increment the address by one since I am saving 32 bits every clock cycle. But the wishbone does not like that it insists on making me increment the address by 4 (as if I am using an 8-bit bus RAM). With this, to save 2 words (of 32 bits each) we need 8 memory locations, have unused 3 memory cells (or 3 words).

Has anyone noticed this phenomen ?
Is there something mising ? For exampple a setting to tell the wishbone that the memory is 32-bit and thus increment by 1.

A.C

Just throw away first two bits when you connect your RAM: some_ram_device some_ram_device_instance(
...
.wb_adr_i(signal_that_increments_by_four[31:2]),
...
);

I would rather say that the bus addresses bytes instead of the words. Many conventional platforms do that even if they require the word-aligned memory access.